Please use this identifier to cite or link to this item:
http://hdl.handle.net/10773/11850
Title: | A novel SAD architecture for variable block size motion estimation in HEVC video coding |
Author: | Nalluri, Purnachand Alves, Luis Nero Navarro, António |
Keywords: | Motion Estimation SAD architecture HEVC |
Issue Date: | 15-Oct-2013 |
Publisher: | IEEE |
Abstract: | Motion estimation (ME) is one of the critical and most time consuming tasks in video coding. The increase of block size to 64x64 and introduction of asymmetric motion partitioning (AMP) in HEVC makes variable block size motion estimation more complex and therefore requires specific hardware architecture for real time implementation. The ME process includes the calculation of SAD (Sum of Absolute Difference) of two blocks, the current and the reference blocks. The present paper proposes low complexity SAD (Sum of Absolute Difference) architecture for ME of HEVC video encoder, which is able to exploit and optimize parallelism at various levels. The proposed architecture was implemented in FPGA, and compared with other non-parallel SAD architectures. Synthesis results show that the proposed architecture takes fewer resources in FPGA when compared with results from non-parallel architectures and other contributions. |
Peer review: | yes |
URI: | http://hdl.handle.net/10773/11850 |
DOI: | 10.1109/ISSoC.2013.6675269 |
Appears in Collections: | DETI - Comunicações |
Files in This Item:
File | Description | Size | Format | |
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IS_SOC2013_Final.pdf | final paper | 322.37 kB | Adobe PDF |
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