Please use this identifier to cite or link to this item:
http://hdl.handle.net/10773/35261
Title: | Analysis and comparison of different approaches to implementing a network-based parallel data processing algorithm |
Author: | Skliarova, Iouliia |
Keywords: | Data processing Parallel algorithm Hardware accelerator High-level synthesis Embedded processor Two smallest values in a dataset |
Issue Date: | 9-Jul-2022 |
Publisher: | MDPI |
Abstract: | It is well known that network-based parallel data processing algorithms are well suited to implementation in reconfigurable hardware recurring to either Field-Programmable Gate Arrays (FPGA) or Programmable Systems-on-Chip (PSoC). The intrinsic parallelism of these devices makes it possible to execute several data-independent network operations in parallel. However, the approaches to designing the respective systems vary significantly with the experience and background of the engineer in charge. In this paper, we analyze and compare the pros and cons of using an embedded processor, high-level synthesis methods, and register-transfer low-level design in terms of design effort, performance, and power consumption for implementing a parallel algorithm to find the two smallest values in a dataset. This problem is easy to formulate, has a number of practical applications (for instance, in low-density parity check decoders), and is very well suited to parallel implementation based on comparator networks. |
Peer review: | yes |
URI: | http://hdl.handle.net/10773/35261 |
DOI: | 10.3390/jlpea12030038 |
Publisher Version: | https://www.mdpi.com/2079-9268/12/3/38 |
Appears in Collections: | DETI - Artigos |
Files in This Item:
File | Description | Size | Format | |
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jlpea-12-00038-v2.pdf | 1.75 MB | Adobe PDF | View/Open |
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