Dynamic jitter accumulation in clock repeaters considering power and ground noise correlations

Abstract

This paper discusses the mechanism behind dynamic jitter accumulation in clock repeaters, considering the impact of power supply noise correlations. We show that differential and common mode noise have a different impact on jitter accumulation, depending on correlations between cascaded repeater stages. We also propose a simple accumulation model that can be used to replace time-consuming transient noise simulations. Besides providing an useful insight regarding the impact of noise correlations on jitter accumulation, the model's accuracy is shown to be within 10% of SPICE results.