Please use this identifier to cite or link to this item:
http://hdl.handle.net/10773/22089
Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Duarte, Luís Medina | pt |
dc.contributor.author | Rodrigues, Luís Abade | pt |
dc.contributor.author | Alves, Luis Nero | pt |
dc.contributor.author | Nogueira, Carlos Gaspar | pt |
dc.contributor.author | Figueiredo, Mónica | pt |
dc.date.accessioned | 2018-02-07T16:24:45Z | - |
dc.date.issued | 2016-09-22 | - |
dc.identifier.isbn | 978-150902526-8 | - |
dc.identifier.uri | http://hdl.handle.net/10773/22089 | - |
dc.description.abstract | This paper addresses the problem of achieving high bandwidth in a DLL design for OFDM based VLC broadcast systems. It describes the implementation of efficient Data Link Layer (DLL) and Forward Error Correction (FEC) modules in a Xilinx FPGA. The proposed DLL aims at furnishing the adequate means to fragment and route both high data-rate (HDR) and moderate data-rate (MDR) service requests while maintaining a continuous transmission flow. The FEC modules aims at providing sufficient error correction capabilities with reasonable computation overheads. Another goal was to develop these modules under a globally asynchronous locally synchronous paradigm, ensuring high modularity and performance. | pt |
dc.language.iso | eng | pt |
dc.publisher | IET/IEEE | pt |
dc.relation | info:eu-repo/grantAgreement/FCT/5876/147328/PT | pt |
dc.rights | restrictedAccess | por |
dc.subject | Visible Light Communications | pt |
dc.subject | Data Link Layer | pt |
dc.subject | FPGA | pt |
dc.subject | MicroBlaze Soft Core | pt |
dc.title | DLL architecture for OFDM based VLC transceivers in FPGA | pt |
dc.type | conferenceObject | pt |
dc.peerreviewed | yes | pt |
ua.publicationstatus | published | pt |
ua.event.date | 20-22, Julho 2016 | pt |
ua.event.type | conference | pt |
degois.publication.location | Prague, Czech Republic | pt |
degois.publication.title | 2016 10th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2016 | pt |
dc.date.embargo | 10000-01-01 | - |
dc.identifier.doi | 10.1109/CSNDSP.2016.7573949 | pt |
Appears in Collections: | DETI - Comunicações IT - Comunicações |
Files in This Item:
File | Description | Size | Format | |
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DLL_FEC_paper_final_reviewed_ieeeeXplorer.pdf | Final version | 907.46 kB | Adobe PDF |
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