Please use this identifier to cite or link to this item: http://hdl.handle.net/10773/8329
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dc.contributor.authorReis, A.D.pt
dc.contributor.authorRocha, J.F.pt
dc.contributor.authorGameiro, A.S.pt
dc.contributor.authorCarvalho, J.P.pt
dc.date.accessioned2012-04-24T16:46:42Z-
dc.date.issued2009-
dc.identifier.isbn978-0-7695-3695-8-
dc.identifier.urihttp://hdl.handle.net/10773/8329-
dc.description.abstractThis work study the PLL (Phase Lock Loop) applied to systems of carrier frequency and data symbols. In each system, we consider four PLL types, namely the analog, hybrid, combinational and sequential.In the synchronizers for carrier frequency, the four PLL (Pll-cf) synchronizes directly with the input carrier.In the synchronizers for data symbols, the four PLL (f+Pll-ds) synchronizes with the data fundamental harmonic, selected by a previous tuning filter.The objective is to study the various synchronizers and evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio).pt
dc.language.isoengpt
dc.publisherIEEEpt
dc.relationFCT/POCI2010pt
dc.rightsrestrictedAccesspor
dc.subjectSynchronism in Digital Communicationspt
dc.titlePhase lock loop used in carrier frequency and in data symbolspt
dc.typeconferenceObjectpt
dc.peerreviewedyespt
ua.publicationstatuspublishedpt
ua.event.date20-25 Julho, 2009pt
ua.event.typeconferencept
degois.publication.firstPage7pt
degois.publication.lastPage10pt
degois.publication.titleICDT '09: 4th International Conference on Digital Telecommunications-
dc.date.embargo10000-01-01-
dc.relation.publisherversionhttp://www.scopus.com/inward/record.url?eid=2-s2.0-70449602412&partnerID=40&md5=3e216b60fb852027b4fa27a9c4b78800pt
dc.identifier.doi10.1109/ICDT.2009.9pt
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