Please use this identifier to cite or link to this item: http://hdl.handle.net/10773/8310
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dc.contributor.authorReis, A.D.pt
dc.contributor.authorRocha, J.F.pt
dc.contributor.authorGameiro, A.S.pt
dc.contributor.authorCarvalho, J.P.pt
dc.date.accessioned2012-04-24T12:15:31Z-
dc.date.issued2008-
dc.identifier.isbn978-0-7695-3162-5-
dc.identifier.urihttp://hdl.handle.net/10773/8310-
dc.description.abstractIn this work, we present the synchronizer as a significant part of a synchronous communication system. At high-speed communication, the synchronous system is advantageous over the asynchronous one, due to its greater transmission efficiency. We begin presenting four synchronizers which are the analog, the hybrid, the combinational and the sequential. All this synchronizers operate at a VCO frequency equal to the transmission rate. After, we present two more sequential versions, operating one at half rate and the other at a quarter rate. Our main objective is to test all this synchronizers in terms of output jitter as function of the input noise.pt
dc.language.isoengpt
dc.publisherIEEEpt
dc.relationFCTpt
dc.rightsrestrictedAccesspor
dc.subjectSynchronism in Digital Communicationspt
dc.titleHigh speed synchronizers operating internally at submultiples ratept
dc.typeconferenceObjectpt
dc.peerreviewedyespt
ua.publicationstatuspublishedpt
ua.event.date8-13 Junho, 2008pt
ua.event.typeconferencept
degois.publication.firstPage91pt
degois.publication.lastPage94pt
degois.publication.titleAICT '08: 4th Advanced International Conference on Telecommunications 2008-
dc.date.embargo10000-01-01-
dc.relation.publisherversionhttp://www.scopus.com/inward/record.url?eid=2-s2.0-50949093762&partnerID=40&md5=e9ddc708c7329366fe3fdf7034b21dccpt
dc.identifier.doi10.1109/AICT.2008.80pt
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