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|Title:||20 Gbit/s DR based timing recovery circuit|
da Rocha, J.R.F.
Digital communication systems
|Abstract:||The design and characterisation of a 20 Gbit/s clock recovery unit developed for the RACE 2011 project of the European Community is reported. This unit is based on an open loop structure using a dielectric resonator (DR) narrowband filter. The jitter results show that the approach provides a robust and low cost solution for the clock extraction problem at very high bit rates|
|Appears in Collections:||DETI - Artigos|
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