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http://hdl.handle.net/10773/18527
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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Farkašová, Katarína | pt |
dc.contributor.author | Farkaš, Peter | pt |
dc.contributor.author | Rakús, Martin | pt |
dc.contributor.author | Rušický, Eugen | pt |
dc.contributor.author | Silva. Adão | pt |
dc.contributor.author | Gameiro, Atílio | pt |
dc.date.accessioned | 2017-10-16T10:41:55Z | - |
dc.date.available | 2017-10-16T10:41:55Z | - |
dc.date.issued | 2015 | - |
dc.identifier.issn | 1335-3632 | pt |
dc.identifier.uri | http://hdl.handle.net/10773/18527 | - |
dc.description.abstract | Error control codes (ECC) as well as translation codes (TC) are used today in many different systems such as computer storages, communications systems and consumer electronic devices. ECC introduce redundancy into the encoded digital sequence in order to decrease the number of errors at output of its decoder [1]. TC introduce redundancy, in order to translate any digital sequence at the input of TC encoder to such output sequence, which fulfills constrains deduced from practical requirements. It is possible to construct codes, which have both of these properties, so called Transcontrol codes or their subclass error control run length limited (ECRLL) codes. In this manuscript a new approach to construction of EC-RLL codes is presented. The new construction is based on some parity check matrix properties of a linear binary block code from which the new EC-RLL code is obtained. | pt |
dc.language.iso | eng | pt |
dc.rights | openAccess | por |
dc.subject | Error control codes (ECC) | pt |
dc.subject | Translation codes (TC) | pt |
dc.subject | Error control run length limited codes | pt |
dc.subject | Modifier | pt |
dc.title | Construction of Error Control Run Length Limited Codes Exploiting Some Parity Matrix Properties | pt |
dc.type | other | pt |
dc.peerreviewed | yes | pt |
ua.distribution | international | pt |
degois.publication.firstPage | 182 | pt |
degois.publication.issue | 3 | pt |
degois.publication.title | Journal of Electrical Engineering | pt |
degois.publication.volume | 66 | pt |
dc.identifier.doi | 10.2478/jee-2015-0030 | pt |
Appears in Collections: | DETI - Artigos |
Files in This Item:
File | Description | Size | Format | |
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peter_farkas.pdf | 131.87 kB | Adobe PDF | View/Open |
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