Photonic integrated transceiver for hybrid PONs

Abstract

On the technology era that we are living, all the citizens of the world are connected in a network. Nowadays, either shopping or meet the most remote place on Earth without leaving home is possible due to the Internet. Because of the proliferation of the services that the Internet provides, the bandwidth and capacity of the networks as they are known are facing their limit. In order to solve this problem, the only solution that the service providers have to properly supply their clients are the optical communications. They allow bitrates in the order of Terabits/s and a reach that can go up to thousands of kilometers. Passive Optical Networks (PONs) are already standardized and deployed by some of service providers. However, they do not use all the fibre capabilities. In order to take full advantage of the fibre capacities, networks that use Wavelength Division Multiplexing (WDM) and advanced modulation formats such as Quadrature Phase Shift Keying (QPSK) must be used. Owing to the growth and evolution of the optical networks, they will become more complex. This complexity will also be at a hardware level that nowadays is still composed by discrete components. The room needed for units such as Optical Line Terminals (OLTs) will be high if integrated optical circuits are not used. Thus, the development of optical networks must be done using Photonic Integrated Circuits (PICs). As a contribution for the development of optical networks of future generations, this work presents the design and implementation of an integrated optical transceiver for PONs with WDM topology that supports advanced modulation formats. These type of networks are called, in the scope of this work, hybrid PONs. At the beginning, a market analysis of the transceivers available is done so that it can be used for comparison and positioning of the developed product. Afterwards, one can read about the theory background of different optical components. For the ones needed on the chip, models are created. The architecture of the transceiver is then presented and divided in three blocks. For each one, its working principle and on chip implementation are presented. At the end, laboratory tests are performed. Their goal is to validate the chip functionalities and architecture.