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 20 Gbit/s DR based timing recovery circuit
Please use this identifier to cite or link to this item http://hdl.handle.net/10773/7058

title: 20 Gbit/s DR based timing recovery circuit
authors: Monteiro, P.
Matos, J.N.
Gameiro, A.
da Rocha, J.R.F.
keywords: Dielectric resonators
Digital communication systems
Optical receivers
Passive filters
Timing circuits
issue date: 1994
publisher: IET
abstract: The design and characterisation of a 20 Gbit/s clock recovery unit developed for the RACE 2011 project of the European Community is reported. This unit is based on an open loop structure using a dielectric resonator (DR) narrowband filter. The jitter results show that the approach provides a robust and low cost solution for the clock extraction problem at very high bit rates
URI: http://hdl.handle.net/10773/7058
ISSN: 0013-5194
publisher version/DOI: dx.doi.org/10.1049/el:19940518
source: Electronics Letters
appears in collectionsDETI - Artigos

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