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|title: ||A test bed for wireless optical LANs|
|authors: ||Aguiar, R.L.|
Alves, L. N.
|keywords: ||Analogue electronics|
Clock recovery circuits
|issue date: ||2001|
|publisher: ||Institute of Electrical and Electronics Engineers (IEEE)|
|abstract: ||This paper presents a test bed for wireless optical LANS. This test bed is flexible, supporting multiple implementation choices. The test bed currently covers all physical layer issues, from FEC coders and LED drivers to front-ends, clock recovery circuits, Viterbi decoders, and sectored receivers. These are implemented with multiple technologies, with DSPs and FPGAs for digital functions, and ASICs and discrete electronics for the analogue electronics. Furthermore, the test bed provides a semi-controlled real life test environment, allowing for close comparison between theoretical and practical results. © 2001 IEEE.|
|publisher version/DOI: ||http://dx.doi.org/10.1109/ICECS.2001.957516|
|source: ||Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems|
|appears in collections||DETI - Comunicações|
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