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 General model for the deployment of time-delay elements in transistorized electronic circuits
Please use this identifier to cite or link to this item http://hdl.handle.net/10773/5210

title: General model for the deployment of time-delay elements in transistorized electronic circuits
authors: Alves, L. N.
Barbosa, L.
Aguiar, R.L.
keywords: Delay cells
Delay elements
Electronic circuits
General model
International conferences
Parasitic effects
Right-Half-Plane (RHP)
Simulation experiments
Time delaying
Time-delay elements
Electron tubes
Networks (circuits)
Time delay
Transfer functions
Delay circuits
issue date: 2006
publisher: Institute of Electrical and Electronics Engineers (IEEE)
abstract: This paper presents a general model for the analysis of time-delay contributions due to right half plane (RHP) zeros in circuit's transfer functions. The presence of these RHP zeros is in general associated to Miller capacitances. These can be explored as a means of implementation of delay elements. A general discussion on the usage of these RHP zeros as means of designing usable delay cells is addressed, including several parasitic effects that may arise in practical implementations. The model is then verified recurring to simulation experiments. © 2006 IEEE.
URI: http://hdl.handle.net/10773/5210
ISBN: 1-4244-0395-2
9781424403950
publisher version/DOI: http://dx.doi.org/10.1109/ICECS.2006.379669
source: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
appears in collectionsDETI - Comunicações

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